1. Field of the Invention:
This invention relates to error injection methods and apparatus used in the testing of electronic data processing systems; and, more particularly, relates to the selective injection of parity errors into data resident within a data processor for testing of error detection and recovery systems.
2. Background Art:
In the past, errors have been injected into electronic circuits by probing circuit nodes to force connected circuitry to certain states indicative of errors. This can be done manually, or automatically. U.S. Pat. No. 4,759,019 to Bentley et al. discloses a programmable apparatus that injects errors by automatically short-circuiting voltage nodes within the system under test to ground or to a supply voltage in response to the system obtaining a particular state. U.S. Pat. No. 4,835,459 to Hamlin et al. describes a computer-controllable external device which, like the Bentley system, injects errors by applying voltage levels to pins or external circuit nodes of the unit under test. Error injection is triggered when a predetermined logic state exists on one or more of the externally-available circuit nodes.
Although straight-forward, the process of injecting errors by shorting circuit nodes can cause damage to circuits if voltage levels are not accurately applied. Moreover, this process is often not possible when highly integrated circuits are being tested, since most circuit nodes are not accessible to external probing devices. One common means of injecting errors into nodes that are not readily accessible involves the use of internal "scan-set" logic. Scan-set logic usually includes a group of internal state devices which are interconnected to one another to form a shift register called a "scan string". Internal circuit nodes can be forced to logic levels by shifting (scanning) data into the scan strings from a device input to simulate an error condition. Generally, this scan will be performed after the system clock has been stopped. After the scan string is initialized to a particular state indicative of an error condition, the system clock is re-started. The injected error condition exercises the error detection and recovery logic.
Several complications exist with using scan strings to inject errors. Prior to injecting most errors using scan strings, the system clock must be halted as discussed above. This must be done at a precise time, so that the circuit is in the same logic state that would exist prior to a particular error occurrence during normal circuit operation. Stopping the clock so that the logic is in an exact state is difficult. Generally, it involves stopping the clock sometime before the logic is in the required state, then issuing single clock pulses until the logic is in the precise state. Calculating the required clock control, then administering that control during circuit test, is time-consuming and error-prone.
Moreover, this process must be repeated for every error injected.
The above-described problems are accentuated when testing very complex circuits such as those associated with pipelined instruction processors. More specifically, testing parity-error detection and recovery logic in pipelined instruction processors has been particularly problematic in prior art systems for several reasons. In pipelined instruction processors, several instructions are in various stages of execution within the instruction processor at one time. If a parity error is detected on an instruction within the instruction processor, the instruction processor completes execution of all foregoing uncompleted instructions in the instruction stream, that is, the pipelined instruction processor is "de-piped". After the instruction processor is de-piped, the instruction which was corrupted is re-fetched from memory. Both the de-pipe and re-fetch processes require very complex logic sequences to perform. These sequences are dependent not only on the type of instructions which are resident in the pipeline at the time of the error, but also on the relative memory address of the re-fetched instruction. Completely testing the error-detection and recovery logic requires the execution of hundreds of error injection test cases. Performing this testing using the scan-set and associated clock control operations described above is very time-consuming. As a result, prior art systems required lengthy test schedules that are no longer feasible considering the short design cycles associated with modern-day development efforts.